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TB32301AFL
TENTATIVE
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB32301AFL
2.4-GHz Radio Communication IC Features
* * Consumption current : 35 mA (typ.) (at reception) : 26 mA (typ.) (at transmission) Operating power supply voltage : 2.7 V to 3.3 V (operating temperature range: -20C to 70C) * * * * Ultra-compact package: 36-pin QON On-chip LNA On-chip VCO On-chip PA Weight: 0.08 g (typ.) Marking: TB32301AFL
Block Diagram
GND GND GND VCC RX2 RX1 IF-IN2 IF-IN1 RX2 RX3 AF2 AF1 D-DATA 27 26 25 24 23 22 21 20 19 28 MIX OUT1 29 MIX FIL 30 VCCRFRX 31 RF IN 32 GNDRF1 33 GNDRF2 34 TXOUT 35 VCCRFTX 36 VCCRF 1 VCC Syn3 2 VCC Syn2 3 4 5 6 7 LD LOOP GND GND GND FIL1 Syn2 Syn3 Syn1 8 REF CLK 9 x2 VCO1 PLL1 DATA SET TX Filter RSSI FM-DET RX LPF 18 RSSI 17 FLLC1 16 VCCRX2 VCCRX2 15 FLLC2 14 BS 13 TXIN 12 STB 11 CLK 10 DATA VCC Syn1
Tuning
This product is sensitive to electrostatic discharge. When handling the product, ensure that the environment is protected against electrostatic discharge.
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TB32301AFL
Pin Functions (typical resistor and capacitor values)
Pin No. 1 2 Pin Name VCCSyn3 VCCSyn2 Power supply pin Power supply pin Function Equivalent Circuit VCCsyn VCO
3
LOOPFIL1
External pin for loop filter
3
GNDsyn
4 5 6
GNDSyn2 GNDSyn3 GNDSyn1
Ground pin Ground pin Ground pin

7 7 LD PLL lock detector output pin
500
GND2
8
REFCLK
Reference clock input pin for PLL, TX filter and IF auto tuning
8
100 k
9 10
VCCSyn1 DATA
Power supply pin Serial data input pin
11
CLK
Serial clock input pin
10 11 12
1 k
12
STB
Serial strobe input pin
13 13 TXIN Transmit signal input pin
1 k
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Pin No. Pin Name Function Equivalent Circuit
14 14 BS Battery-saving pin
1 k
Internal reference voltage
15
Receive LPF (next stage of demodulator)
Internal filer for transmit data
15, 17
FLLC2 FLLC1
Auto-tuning pin. External capacitor determines the time constant of auto-tuning circuit.
IF input stage internal BPF
FSK detection filter
17
FLL detector
16
VCCRX2
Power supply pin
18
RSSI
This pin drives out DC voltage according to the RF input signal level.
18 45 k 19 500
19
DDATA
Comparator output pin 10 k
20
AF1
Demodulation signal output pin
20
3
100
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TB32301AFL
Pin No. 21 Pin Name VCCRX1 Power supply pin Function Equivalent Circuit
100 k 3 k
22 10 k 22 AF2 Comparator input pin 10 k
23 24
GNDRX2 GNDRX1
Ground pin
25 IF amplifier input pin
360
25
IFIN1
26
IFIN2
26
27
GNDRF3
Ground pin
28
MIXOUT1
Mixer output pin
28
450
360
2.9 k
29
MIXFIL
Mixer filter pin
29
30
VCCRF1
Power supply pin
31 31 RFIN RF signal input pin
4 k
4
2 k 50 A
2 k
1 M
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TB32301AFL
Pin No. 32 33 34 35 36 Pin Name GNDRF1 GNDRF2 TXOUT VCCRF2 VCCRF3 Ground pin RF signal output pin Power supply pin Power supply pin Function Equivalent Circuit
Note: The equivalent circuit diagrams above are intended as an aid for designing external circuits. They do not show the exact layout of the internal circuits.
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Power Supply
Power Supply Name VCCSyn3 VCCSyn2 VCCSyn1 VCCRX2 VCCRX1 VCCRFRX VCCRX TX Pin No. 1 2 9 16 21 30 Ground Relevant Pin Name GND Syn3 GND Syn2 GND Syn1 GND RX3 GND RX2 GND RF1 GND RF2 GND RX1 GND RF1 GND RF2 GND RX1 GND RF1 GND RF2 Pin No. 5 2 6 23 24 32 33 27 32 33 27 32 33 VCO Doubler VCO1 PLL, DATA SET Tuning (FLL), RX-AMP, RX-LPF, DATA COMP, FM-DET TX-FILTER, PA, RSSI, IF-AMP, (IF-BPF) LNA Block Name
35
PA
VCCRF
36
PA, MIXER, LNA
Supplementary: Pins as shown below are shorted together. (1) VCC RX TX (35 pin) - VCC Syn2 (2 pin) (2) VCC RF (36 pin) - VCC RFRX (30 pin)
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Functions and Operation
1. Serial data input timing chart
* Data to control the TB32301AFL is serially applied to pins CLK, DATA and STB. * Data is loaded into shift registers with MSB first on the rising edge of the clock and latched on the rising edge of the STB signal. When the STB pin is high, the data stored in the shift register is retained even if clock is applied. When the STB pin is low, the data can be rewritten. * Input timings of the CLK, DATA and STB are shown below.
> 0.05 s = CLK > 0.02 s = DATA > 0.02 s = STB > 0.1 s = > 0.01 s = > 0.02 s = > 0.02 s =
2. Serial data control contents
The TB32301F has five types of control contents. These types are determined by serial input 5-bit register address (group code). The control contents consist of PLL main counter setting, PLL reference counter setting, auto-tuning reference counter setting, transmit power amplifier gain setting and system control setting. These settings are controlled independently one another.
2.1
Register address setting table (group code)
GC4 0 0 0 0 0 GC3 0 0 0 0 0 GC2 0 0 0 0 1 GC1 0 0 1 1 0 GC0 0 1 0 1 0 PLL main counter setting PLL reference counter setting Auto-tuning reference counter setting Transmit power amplifier gain setting System control register setting Control Contents
2.2
PLL main counter setting
* The PLL main counter employs a swallow counter. * It consists of 6-bit swallow counter, 9-bit programmable counter and 1/64, 1/65 2-modulus prescaler. * The divide factor can be set in the range 4032 to 32767 by sending any data to the swallow counter and the programmable counter.
MSB 1 0 1 0 0 0 0 0 0 N8 N7 N6 N5 N4 N3 N2 N1 N0 A5 A4 A3 A2 A1 A0 0
Group code
Programmable counter: N
Swallow counter: A
A = A0 + A1 x 21 + A2 x 22 + --------- + A5 x 25 N = N0 + N1 x 21 + N2 x 22 + -------- + N8 x 28 (Divide factor) = 64N + A 4032 < (Divide factor) < 32767 = =
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2.3 PLL reference counter setting
* The PLL reference counter generates phase comparison frequency0. * It consists of 9-bit reference counter. The divide factor can be set in the range 4 to 511 by sending any data to the reference counter.
MSB 1 0 1 0 0 0 0 0 1 R8 R7 R6 R5 R4 R3 R2 R1 R0 0 0 0 0 0 0 0
Group code
Auto-tuning counter: F
R = R0 + R1 x 21 + R2 x 22 + --------- + R8 x 28 (Divide factor) = R 4 < (Divide factor) < 511 = =
2.4
Auto-tuning reference counter setting
* The TB32301AFL has an automatic tuning system to correct the fluctuation of center frequency in FM detector, which is caused by, for example, temperature change. To generate a reference clock to correct the fluctuation, set the divide factor of auto-tuning reference counter to the value to obtain 200-kHz frequency, according to external reference clock frequency. * The auto-tuning reference counter consists of 8 bits. * The divide factor can be set in the range 6 to 255 by sending any data to the reference counter. F = F0 + F1 x 21 + F2 x 22 + --------- + F7 x 27 (Divide factor) = F 6 < (Divide factor) < 255 = =
MSB 1 0 1 0 0 0 0 1 0 F7 F6 F5 F4 F3 F2 F1 F0 0 0 0 0 0 0 0 0
Group code
Auto-tuning counter: F
Internal control bits (always 0) (Note)
Note
Internal control bits are used to control the PLL. Please clear the bits. Otherwise, the PLL may not operate properly.
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2.5 Transmit power amplifier setting
Applying data serially to pins CLK, DATA and STB changes the gain of the transmit power amplifier. The power control counter consists of 5 bits.
MSB 1 0 1 0 0 0 0 1 1 P4 P3 P2 P1 P0 0 0 0 0 0 0 0 0 0 0 0
Group code
Power control counter: P
(Control step number) = P0 + P1 x 21 + P2 x 22 + --------- + P4 x 24
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2.6 System control register setting
In the system control register, applying data serially to pins CLK, DATA and STB sets the optional functions as described below.
MSB 1 0 1 0 0 0 1 0 0 CP CP 2 1 0 MO PD PD PD (M1) (M2) (M3) (M4) 0 D 3 2 1 0 0 0 0 0 0 DC DC 2 1
Group code
Charge Transmit Battery-saving Transmit modulation pump current modulation (power-down) control setting control control
(Note)
Comparator control
Note: Please clear the bits. * PLL charge pump current setting (CP1 and CP2 bits: 2.4 GHz) The TB32301AFL contains a constant current charge pump circuit. The output current of the circuit can be selected by setting the CP1 and CP2 bits.
CP2 0 0 1 CP1 0 1 0 Charge Pump Current 4 mA 2 mA 1 mA
* Transmit data timing setting (MOD bit) Clearing the MOD bit makes the VCO circuit oscillate at the center frequency, which is controlled by the PLL. The circuit is not controlled by received data.
MOD 0 1 Transmit Data Timing Modulator OFF Modulator ON
* Battery-saving (power-down) mode setting (PD1, PD2 and PD3 bits) Setting the PD1, PD2 and PD3 bits controls the circuits in the reception and transmission blocks. The settings of the external BS control pin (14 pin) and the control bits are shown in the table below.
BS Control Bits PD3 L H H H H H H * 1 1 1 0 0 0 PD2 * 1 0 0 0 0 1 PD1 * 1 0 1 1 0 1 LNA OFF OFF OFF OFF OFF ON OFF MIX OFF OFF OFF OFF OFF ON OFF Reception Block IF-AMP OFF OFF OFF OFF OFF ON OFF FM-DET RX-LPF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF ON OFF Transmission Block PA OFF OFF OFF ON OFF OFF OFF TX-LPF OFF OFF OFF ON ON OFF OFF Common Block PLL, VCO OFF OFF ON ON ON ON OFF Auto tuning OFF OFF ON ON ON ON ON
* Transmit modulation control bits (M1 to M4 bits) M1 to M4 bits are cleared for normal operation, however, M2 to M4 bits can be set to high to control the transmit modulation as shown below.
M1 0 0 M2 0 1 M3 0 1 M4 0 1 Transmit Modulation Normal modulation Normal modulation x 16/8
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* Rise time constant setting of comparator reference level (D1 and D2 bits) The rise time constant of data comparator reference level is determined by an external capacitance and an internal resistance. The internal resistance can be selected by applying data serially to pins CLK, DATA and STB. (Rise time constant) = (External capacitance: C) x (Internal resistance: R)
DC2 0 0 1 1 DC1 0 1 0 1 Internal Resistance: R 10 k 10 k 100 k 1000 k
3. Image canceller mixer in reception block
The TB32301AFL contains an image canceller mixer as the first stage of the reception block. The image canceller mixer is designed for upper local, therefore, please set the local signal frequency to f0 (desired reception frequency) + 11 MHz (IF frequency).
4. Lock detector function (LD pin: 7 pin)
The TB32301AFL incorporates VCO lock detector function. When a phase error is detected in the phase comparator, 0 is driven out from the LD pin. When the VCO is locked or all the circuits are OFF, 1 is driven out from the pin.
5. VCO modulation polarity and demodulation data polarity
* VCO modulation polarity
Transmit Data 1 0 VCO Frequency Deviation Positive (+) polarity Negative (-) polarity
* Demodulation data polarity The polarity of the data, which is demodulated by the FM detector and the data comparator, is the same as that of transmit data.
At Transmission Transmit Data 1 0 At Reception FM Detector Positive (+) polarity Negative (-) polarity Data Comparator Output 1 0
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Electrical Characteristics
Maximum Ratings
Characteristics Power supply voltage Power dissipation Input pin voltage Storage temperature range Symbol VCC_A, VCC_D PD CLK, DATA, STB, BS, LD,TXIN Tstg Rating 3.6 530 3.6 -50 to 150 Unit V mW V C
Note 1: Maximum ratings are a set of specified parameter values which must not be exceeded during operation, even for an instant.
Operating Ratings
Characteristics Operating voltage Operating temperature Symbol Vopr1 Topr1 Test Circuit Test Condition Ta = 25C, ground reference Rating 2.7 to 3.3 -20 to 70 Unit V C
Note 2: These ratings specify the ranges within which the device can operate its basic functions, even when fluctuations in its electrical characteristics occur.
Electrical Characteristics
(Unless otherwise specified, Ta = 25C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA bit setting = 21, Dev = 160 kHz) Power Supply
Characteristics Current consumption 1 at no signal Symbol ICC1 Test Circuit 1 Test Condition At reception BS = H, PD1 = 0, PD2 = 0, PD3 = 0 (Note 3) At transmission BS = H, PD1 = 1, PD2 = 0, PD3 = 1 (Note 3) In battery-saving mode BS = L, PD1 = 1, PD2 = 1 PD3 = 1 (Note 3) CLK, DATA, STB, BS, TXIN CLK, DATA, STB, BS, TXIN Min 28.0 Typ. 35.1 Max 42.0 Unit mA
Current consumption 2 at no signal
ICC2
1
19
25.6
42
mA
Supply current at no signal
ICCQ1
1
VCC x 0.8 -0.2
0
10 VCC + 0.2 VCC x 0.2
A
High-level input voltage Low-level input voltage
VIH VIL

VCC 0
V V
Note 3: Please refer to Section 2.6 "System control register setting".
Integrated Characteristics
Characteristics Minimum input level Demodulation output level Symbol VIN(min) Vod Test Circuit 1 Test Condition S/N = 20dB Vin (LNA) = 70dBV Min - Typ. 20.4 450 Max - - Unit dBV mVp-p
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Electrical Characteristics
(Unless otherwise specified, Ta = 25C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA = 21 setting, Dev = 160 kHz) LNA and Mixer Blocks
Mixer image rejection ratio Output impedance Output capacitance Operating frequency range (LNA and mixer) Intercept point 1 output (LNA and mixer) IRR R-OUT (MIX) C-OUT (MIX) Fopr (LNA + MIX) OIP3-1 (LNA + MIX) 1 1 f1 (UD1) = 2453 MHz, UD1: No modulation f2 (UD2) = 2456 MHz, UD2: No modulation 20 2400 33 470 2 2500 dB pF MHz
85
dBV
IF Amplifier, DET and RX-LPF Blocks
RSSI output voltage 1 RSSI output voltage 2 IF amplifier input impedance IF amplifier input capacitance V (RSSI-1) V (RSSI-2) R-IN (IF) C-IN (IF) 1 1 Vin (IF) = 41dBV, No modulation Vin (IF) = 91dBV, No modulation 0.36 (1.25) 0.54 (1.75) 720 2 0.72 (2.25) V V pF
Comparator
Duty ratio High-level leakage current Output ON resistance COMP (duty) I (COMP-LEAK) R (COMP-L) 1 1 Open-drain output Internal time constant setting 1 (10 k) Open-drain output IL = 100 A 40 50 0 1 60 5 % A k
PLL Block
Lock-up time t-lock 1 Phase comparison frequency: 500 kHz Charge pump output current = 4 mA 150 s
Reference clock operating frequency range Reference clock input level range Clock (serial data) input frequency Charge pump output current 1 Charge pump output current 2 Charge pump output current 3 Charge pump output current 4 LD OFF leakage current LD ON resistance
fxin vxin fclk Icp (1) Icp (2) Icp (3) Icp (4) LD-off-LEAK R(LD-on)
1 1 1 1 1 1 1 1 1 Vcp = 1/2VCC Vcp = 1/2VCC Vcp = 1/2VCC Vcp = 1/2VCC Open-drain output Open-drain output
4 92 350 0.7 1.4 2.8
100 500 1 2 4 0 1
20 112 20 650 1.3 2.6 5.2 5
MHz dBV MHz A mA mA mA A k
VCO Block
VCO Oscillation frequency range (x 2) VCO gain (x 2) VCO phase noise (x 2) f (VCO) Kv pn1 pn2 1 @500 kHz @2 MHz 2400 120 107 119 2500 MHz MHz/V dBc/Hz dBc/Hz
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TB32301AFL
Electrical Characteristics
(Unless otherwise specified, Ta = 25C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA = 21 setting, Dev = 160 kHz) Transmission Block
Tx data input level Local leakage spurious Maximum frequency deviation Vtx SPRlo dev (tx) 1 1 Test frequency: 1.225 GHz On loop, fBB=100kHz (CW) VCC x 0.8 (140) VCC -30 (190) VCC + 0.2 -20 (230) dBm KHz
PA Block
Nominal output signal level Minimum output signal level Output impedance PA-OUT (nom.) PA-OUT (min.) Z-OUT (PA) 1 1 1 DATA21 set for PA output DATA3 set for PA output (-9) (-3) (-30) 50 (-25) dBm dBm
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TB32301AFL
Test Circuit 1
ICC1, ICC2, ICCQ A VCC = 3.0 V
VOD V
VIN (min) BER
C211 1000 pF
C212 0.1 F
C201 0.1 F C271 1000 pF
R201 1 k C202 300 pF R191 10 k 20 19 D-DATA 18 RSSI 17 FLLC1 VCC RX3 16 C171 0.01 F C181 1000 pF V (RSSI-1) V (RSSI-2) V
R281 200 28 VCCRFRX C302 1000 pF SG fin = 2450 MHz C301 10 pF L311 4.7 nH C311 22 pF C29A 0.01 F 29
MIX OUT
27
GND RX1
26
IF-IN2
25
IF-IN1
24
GND RX2
23
GND RX3
22
AF2
21
VCC RX2
AF1
MIX FL
IF BPF
FM-DET
RX LPF
30 VCCRFRX 31 RF IN RSSI
Tuning (FLL)
32 GNDRF1 C343 1000 pF PA - OUT V C342 10 pF L341 4.7 nH 34 35 VCCRFTX 36 VCCRF VCC Syn3 1 33 GNDRF2 TXOUT x2 VCO1 PLL1 DATA SET
C162 1 F C15A C161 0.01 F 15 0.01 F FLLC2 R71 10 k 14 BS TX LPF 13 TXIN 12 STB 11 CLK 10 DATA 9 R101 100 k R101 100 k R101 100 k R101 100 k
C341 10 pF C352 1000 pF C351 10 pF C361 1000 pF C362 10 pF
VCC Syn2
2
LOOP FIL1
3
GND Syn2 C32 R31 10 nF 2.7 k
4
GND Syn3
5
GND Syn1
LD 6 7
REF CLK
8
VCC Syn1
C31 4.3 nF
C11 10 pF
C21 10 pF
C12 100 pF
C22 100 pF
C91 10 pF
R71 10 k
C81 100 pF
(1)
Detailed test condition of minimum input level in the integrated characteristics * Detector LPF: C202 = 300 pF, R201 = 1 k and fT = 530 kHz * Total bits: 1.6 Mbits * Data comparator output: Monitors using a probe. * Input/output: LNA input, data comparator output * Transmission modulation (DEV): 157.5 kHz * Data: PRBS9 (1MBPS) * BT = 0.5 gaussian filter * IF filter used. (Note) * Tested using a Toshiba's mounting board
Note: Ceramic filter manufacturer and product no. SFSCB11M0WF manufactured by Murata Manufacturing Co., Ltd. (2) Detailed test condition in the transmission block * Tested using a Toshiba's mounting board Detailed test condition of output level in the PA block * Tested using a Toshiba's mounting board
(3)
C92 100 pF SG fin = 13 MHz, 100 mVrms
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TB32301AFL
Package Dimensions
Weight: 0.08 g (typ.)
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TB32301AFL
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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